With an integrated circuit (IC) package as a semiconductor IC device, static electricity charged on a human body, for example, may be discharged through lead pins of the IC package, thus leading to physical failure or breakdown of the IC. To prevent such failure or breakdown due to static electricity, a semiconductor IC device having a static protection circuit provided on a silicon chip within the IC package is known.
FIG. 1 shows such a static protection circuit 2 formed on a silicon chip. The static protection circuit 2 is formed between a Vdd bus line 3 for providing power supply to circuit elements (not shown) disposed on the silicon chip and a GND (ground) bus line 4. The Vdd bus line 3 is arranged to receive an external power supply from a Vdd lead pin of the IC package via wire W and pad Pd. The static protection circuit 2 is formed near the pad Pd.
Such a static protection circuit 2 is comprised of an N-channel FET (field effect transistor) 21. A drain terminal D and a source terminal S of the N-channel FET 21 are connected to the Vdd bus line 3 and GND bus line 4, respectively, while its gate terminal is connected to the source terminal S.
With such an arrangement, when an overvoltage is applied across the Vdd bus line 3 and GND bus line 4 via the lead pin of the IC package due to electrostatic discharge, the resulting overvoltage is applied across the drain terminal D and source terminal S of the N-channel FET 21, resulting in a breakdown of the N-channel FET 21. This immediately renders the N-channel FET 21 conductive, thus shorting the Vdd bus line 3 and GND bus line 4. Therefore, the overvoltage-induced current is absorbed through a path from the Vdd bus line 3 to the N-channel FET 21 to the GND bus line 4, thereby preventing the overvoltage-induced current from flowing into the circuit elements.
The operation of a static protection circuit adapted to an integrated circuit driven by a single power supply (Vdd) has been described above; now, the operation of a static protection circuit adapted to an integrated circuit driven by multiple power supplies with different voltages will be described below.
FIG. 2 shows a configuration of a static protection circuit adapted to an integrated circuit driven at two different types of power supply voltages, Vdd1 and Vdd2. A Vdd1 bus line 7 receives a power supply of a first power supply voltage Vdd1 from a Vdd1 lead pin of the IC package via wire W and pad Pd. On the other hand, a Vdd2 bus line 8 receives a power supply of a second power supply voltage Vdd2 from a Vdd2 lead pin of the IC package via wire W and pad Pd. A static protection circuit 2a is comprised of N-channel FETs 21 and 22. A drain terminal D and a source terminal S of the N-channel FET 21 are connected to a Vdd1 bus line 7 and a GND bus line 4, respectively, while its gate is connected to the source terminal S. On the other hand, a drain terminal D and a source terminal S of the N-channel FET 22 are connected to a Vdd2 bus line 8 and the GND line 4, respectively, while its gate terminal is connected to the source terminal S.
With such a configuration, when an overvoltage is applied between the Vdd1 bus line 7 and GND bus line 4 due to electrostatic discharge, the N-channel FET 21 of the static protection circuit 2a breaks down. This immediately renders the N-channel FET 21 conductive, thus shorting the Vdd1 bus line 7 and GND bus line 4. Therefore, because the overvoltage-induced current is absorbed by a path from the Vdd1 bus line 7 to the N-channel FET 21 to the GND bus line 4, the resulting overvoltage-induced current is prevented form flowing into the circuit elements. On the other hand, when an overvoltage is applied between the Vdd2 bus line 8 and GND bus line 4 due to electrostatic discharge, the N-channel FET 22 of the static protection circuit 2a breaks down. This immediately renders the N-channel FET 22 conductive, thus shorting the Vdd2 bus line 8 and GND bus line 4. Therefore, because the resulting overvoltage-induced current is absorbed by a path from the Vdd2 bus line 8 to the N-channel FET 22 to the GND bus line 4, this overvoltage-induced current is prevented from flowing into the circuit elements.
Additionally, when an overvoltage is applied between the Vdd1 bus line 7 and Vdd2 bus line 8 due to electrostatic discharge, one of the N-channel FETs 21 and 22 which has a higher potential breaks down, causing the FET with a lower potential to be forward for a parasitic diode. This immediately renders both the N-channel FETs 21 and 22 conductive, thus shorting the Vdd1 bus line 7 and GND bus line 4, and the Vdd2 bus line 8 and GND bus line 4, respectively. As a result, the afore-described overvoltage-induced current flows along a path comprised of the Vdd1 bus line 7, N-channel FET 21, GND bus line 4, N-channel FET 22 and Vdd2 bus line 8.
However, since the current due to overvoltage of electrostatic discharge first flows into a section (P) of the GND bus line 4, there is a problem that the resulting overvoltage-induced current flows into circuit elements (not shown) connected onto this section (P) of the GND bus line 4, thus damaging the elements.
The present invention is intended to solve such problems, and it is an object of the present invention to provide a static protection circuit for a semiconductor integrated circuit device, which permits static protection for an IC circuit driven on a plurality of power supplies having different voltages.
A static protection circuit for a semiconductor integrated circuit according to the present invention includes a plurality of power supply lines for supplying different power supply voltages and a GND line, said static protection circuit comprising first and second transistors each having two controlled terminals connected to each of said power supply lines and said GND line, respectively, and a control terminal connected to one of said controlled terminals; and a third transistor having controlled terminals connected to each of said power supply lines, and a control terminal to which a nonconductive voltage is applied.